CMOS structures comprise complementary mated pairs of field effect transistors of differing conductivity type. Due to the use of complementary mated pairs of differing conductivity type, CMOS structures also provide for reduced energy or power consumption.
A trend within CMOS fabrication is the use of stressed layers as a means to produce a mechanical stress or strain field within a channel region of a CMOS transistor; the channel region of a CMOS transistor is typically located within a semiconductor substrate beneath the gate conductor. Certain types of mechanical stresses are desirable insofar as they introduce a stress into a semiconductor channel. Such a stress generally provides for enhanced charge carrier mobilities within a CMOS transistor. Complementary types of channel stress (i.e., tensile or compressive stress or strain in the direction of electrical current) enhance complementary types of charge carrier mobility (i.e., electron or hole) within complementary types of CMOS transistors (i.e., nFET or pFET).
Since mechanical stress is a significant factor that may considerably improve field effect transistor performance, CMOS structures and methods that provide for enhanced levels of mechanical stress within CMOS transistor channels are desirable.
Methods for improving charge carrier mobility within CMOS structures that include pFET and nFET devices are known in the semiconductor fabrication art. For example, dual stress liner (DSL) technology has been demonstrated as an efficient and economical method to enhance CMOS device performance in 90 nm and 65 nm semiconductor-on-insulator (SOI) technology; see, for example, U.S. Patent Application Publication No. 2005/0093030 A1 to Doris et al., H. S. Yang et al., IEDM 2004, p. 1075 and E. Leobandung et al. VLSI 2005, p. 126-127.
At the DSL boundary, it is preferred to have an overlap area between the tensile and compressive nitride liners in order to obtain good protection for the underlying devices. However, with aggressive scaling of contacted gate pitch, it becomes more difficult to deal with DSL boundaries, especially for etching contact-to-active-area (CA) holes. For example, the DSL overlap could be located on a polygate gate-landing pad that connects the nFET and pFET gates together (e.g., an inverter) or near source/drain (S/D) contact areas. In this case, it is required that the two stress nitride liners (i.e., tensile and compressive liners) have to be etched through during later CA hole etching.
In addition to the above, current technology provides a large aspect ratio between the height of the gate liner top and the pitch of the gate electrode which makes it difficulty to etch a contact hole by reactive ion etching due to thickness variation in the interlevel dielectric material.
Another example is related to DSL overlap that is on the top of a dummy gate. The dummy gate is widely used to improve gate patterning and is located on a shallow trench isolation (STI) region between neighboring nFETs and pFETs. Usually, resistance of the S/D contact areas near the dummy gate is very sensitive to the misalignment of the DSL boundaries in 65 nm technology.
It will become even more difficult to deal with DSL boundaries when CMOS technology scales down to 45 nm and beyond due to tighter CMOS ground rules. Therefore, it would be desirable to provide methods and CMOS structures in which the negative impact of DSL boundaries can be minimized without degrading CMOS performance and causing an area penalty.